An energy efficient and area saving local clocking scheme using new resonant techniques is illustrated with a bank of 1024 flip-flops. Energy recovering pulsed resonant (PR) clocking is designed to drive explicit-pulsed negative setup time latches. A pre-driver that generates tracking pulses at each transition of clock for dual edge (DET) operation is robust across PVT. While both the pre-driver and driver use inductors for energy reduction and recycling, the inductor area is small enough to fit over the active circuitry resulting in 40% power and active area reductions. The pulsed resonance (PR) operation needs only 1/10 th the inductance of conventional LC resonant circuits. Monte Carlo simulations using 45nm device and interconnect models show that the design supports Dynamic Voltage and Frequency Scaling from 2GHz@1.3V to 200MHz@0.5V.