Quantum dot Cellular Automata (QCA) is an emerging nanotechnology paradigm that is currently being investigated as a possible CMOS substitute. It offers higher speed and lower area and power consumption than CMOS transistors. However, due to its intrinsic pipelined nature, QCA circuits suffer from serious throughput reductions due to feedback signals. As a consequence to fully exploit the true potential of this technology, circuits architecture must be designed with the aim to reduce or eliminate the presence of feedbacks. This work proposes as a relevant design case, the QCA implementation of Fast Fourier Transform (FFT) Algorithm. A novel architecture for partial parallel FFT processor is presented which not only reduces the circuit complexity but also eliminates the need of feedback signals, allowing to maximize the throughput. The proposed architecture is described using an accurate, layout aware VHDL model which is exploited in a hierarchical bottom up approach to evaluate the logical behavior, area and power dissipation of whole design. This innovative approach widely expands the field of application for QCA circuits.