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Low-voltage CMOS voltage squarer

descriptionPublicationkeyboard_double_arrow_right Article 01 Dec 2009Publisher:IEEEJournal:2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)

Authors: Spyridon Vlassis; George Raikos;

doi: 10.1109/icecs.2009.5410960

Low-voltage CMOS voltage squarer

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Abstract

A voltage squarer based on bulk-driven PMOS transistors is proposed in this paper. Circuit topology employs a voltage attenuator and the quadratic I D /V G characteristic of a MOS in saturation. The squarer was designed with a 0.8V supply voltage using standard 0.35um CMOS process, which offers large value of threshold voltage. The squarer topology was modified for 0.18um CMOS process, which threshold voltage was smaller, operating under the extreme low supply voltage of 0.5V. The output current is proportional to square of the input voltage in each case. Simulation results verify the theoretical analysis demonstrating small relative error and fast transient response.

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