The advancement in the designing of multicores system-on-chip pose the requirement of communication infrastructure which provides target performance to meet the computation requirement of gigascale processors. Thus a promising solution called LAWI, a Load balanced Architecture for Wireless Network on chip, has been proposed to bridge the widening gap between the communication efficiency and computation requirements of gigascale system-on-chip devices. It comprise of intelligent router that balances the traffic load across long distance transmission and reduces the congestion delay. An efficient low-cost deadlock-free routing scheme LAWIXY has been proposed that reduces the network congestion and hence improves performance of wireless network on chip. It is demonstrated that LAWI outperforms its counterpart network architectures and improves performance for larger system size.