The experimental results from a fabricated integrated circuit of fractional‐order capacitor emulators are reported. The chip contains emulators of capacitors of orders 0.3, 0.4, 0.5, 0.6 and 0.7 with nano‐Farad pseudo‐capacitances that can be adjusted through a bias current. Two off‐chip capacitors are used to set the bandwidth of each emulator independently. The chip was designed in Austria microsystems (AMS) 0.35μ CMOS.