Abstract A probing technique to obtain the energy distribution of positive charges in high-k gate stack dielectrics, both within and beyond the substrate bandgap, has been proposed. The energy distribution of different high-k devices has been investigated and attention has been paid to their differences from the single-layered SiON devices. The results obtained from the technique demonstrate the existence of different types of positive charges with each type of them dominating a different energy region. It is observed that the positive charges in high-k stacks are dominated by the as-grown hole traps below the valence band and the cyclic positive charges within the bandgap. The increase in the cyclic positive charges in thinner high-k devices suggests higher NBTI for future CMOS technologies. It is also observed from the energy profile that the metal gate can impact the NBTI substantially. The energy profile obtained from this technique clearly indicates that process optimization is essential for minimizing NBTI in the high-k gate stacks.