Abstract Spin Transfer Torque Magnetic RAM (STT-MRAM) promises low power, great miniaturization prospective (e.g. 22 nm) and easy integration with CMOS process. It becomes actually a strong non-volatile memory candidate for both embedded and standalone applications. However STT-MRAM suffers from important failure and reliability issues compared with the conventional solutions based on magnetic field switching. For example, a read current could write erroneously the stored data, the variability of ultra-thin oxide barrier drives high resistance variation and the injected current in the nanopillar induces lower lifetime etc. This paper classifies firstly all the possible failures of STT-MRAM into “soft errors” and “hard errors”, and analyzes their impact on the memory reliability. Based on this work, we can find some efficient design solutions to address respectively these two types of errors and improve the reliability of STT-MRAM.