Abstract The multiple network-on-Chip (multi-NoC) architecture is an attractive solution to scale on-chip network bandwidth; however, its performance is influenced by its overall communication infrastructure. Incorporating wireless links attract the traffic and cause the power-gated components to stay in sleep state for a longer period of time. The presented research proposes a system generating discrete frequencies via a series of microring resonators to generate frequency channels with 200 MHz Full Width at Half Maximum (FWHM) and 2.5 GHz free spectral range (FSR) for wireless-assisted multi-NoC application. It also evaluates the proposed architecture tested with a 64-core processor with a mesh topology using synthetic traffic and the PARSEC benchmark. The results show that the average network power of the proposed architecture is 55.4% and 11.1% lower than traditional single-NoC and power-gating multi-NoC designs respectively. Furthermore, evaluation of network latency shows that the proposed architecture has an average reduction by 10.4% in comparison with power-gated multi-NoC design.