Low-order (first- and second-) ΣΔ modulation-based A/D converters [Agra83] [Cand85] [Inos62] [Leun88] [Plass78] are very interesting for mixedsignal applications due to their small analog circuitry content, robustness and easy implementation. The second-order architecture [Agra83] [Bose88b] [Cand85] is preferred to the simpler first-order one because it is less sensitive to the correlation between the input and the quantization noise, which reduces the presence of pattern noise [Cand81], and has been largely used in various industrial applications. In any case, to reach a given resolution the oversampling ratio (M) must be kept constant, so that an increase in bandwidth implies a proportional increase in the clock frequency. For example, if a 16bit resolution, is required for a second-order architecture, M must equal at least 256, which for a 2-kHz bandwidth (typical in energy metering systems) pushes the clock frequency up to 1.024MHz. In audio band (20kHz), a 10.2MHz clock rate would be needed, while for video, up to 5MHz, 2.56GHz! Apart from the necessary increase in power consumption, increasing the clock frequency generates additional problems such as jitter, switching noise, etc.