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De-RISC: Dependable Real-time RISC-V Infrastructure for Safety-critical Space and Avionics Computer Systems

Authors: Gómez-Molinero, Francisco; Masmano, Miguel; Nicolau, Vicente; Wessman, Nils-Johan; Andersson, Jan; Le Rhun, Jimmy; Cabo, Guillem; +3 Authors

De-RISC: Dependable Real-time RISC-V Infrastructure for Safety-critical Space and Avionics Computer Systems

Abstract

{"references": ["RISC-V Foundation. https://riscv.org/, accessed in May 2021.", "Cobham Gaisler. \"NOEL-V Processor\", https://www.gaisler.com/noel-v, accessed in May 2021.", "fentISS. \"XtratuM\", https://fentiss.com/products/hypervisor/, accessed in May 2021.", "\"De-RISC: Dependable Real-time Infrastructure for Safety-critical Computer\", http://www.derisc- project.eu/, accessed in May 2021.", "Paco G\u00f3mez Molinero, Javier Coronel Parada, Miguel Masmano Tello, \"XtratuM: A space qualified Hypervisor for LEON-based Computers\", GR740 User Day at ESTEC, 28th November 2019.", "Cobham Gaisler. \"GR740 Quad-Core LEON4 SPARC V8 Processor\", https://www.gaisler.com/gr740, accessed in May 2021.", "fentISS, \"LithOS\", https://fentiss.com/products/lithos/, accessed in May 2021.", "Enrico Mezzetti, Leonidas Kosmidis, Jaume Abella, Francisco J. Cazorla, \"High-Integrity Performance Monitoring Units in Automotive Chips for Reliable Timing V&V\", in IEEE Micro, vol. 38, no. 1, pp. 56- 65, January/February 2018.", "Javier Jalle, Mikel Fernandez, Jaume Abella, Jan Andersson, Matthieu Patte, Luca Fossati, Marco Zulianello, Francisco J. Cazorla, \"Contention-aware performance monitoring counter support for real-time MPSoCs\", 2016 11th IEEE Symposium on Industrial Embedded Systems (SIES), Krakow, 2016, pp. 1-10.", "L. Pomante, D. Andreetti, F. Federici, V. Muttillo, D. Pascucci, \"Analysis and design of a Command & Data Handling platform based on the LEON4 multicore processor and PikeOS hypervisor\", DAta Systems In Aerospace \u2013 DASIA 2017.", "Julien Galizzi, Jean-Jacques Metge, Paul Arberet, Eric Morand, Fabien Vigeant, et al.. \"LVCUGEN (TSP-based solution) and first porting feedback\", Embedded Real Time Software and Systems (ERTS2012), Feb 2012, Toulouse, France."]}

The world market for aviation and space computing systems faces a significant shift caused by the loss of momentum of the traditionally used PowerPC and SPARC instruction set architectures in the commercial domain. This means that the space industry is not able to leverage training, software tools, etc. from the commercial domain and this fuels a need to shift to architectures present in larger commercial markets. The De-RISC project brings together leading European entities within the areas of fault-tolerant microprocessors, hypervisors, embedded safety-critical software and mixed-criticality systems in an effort to commercialize a complete technology stack consisting of an FPGA space grade development board, system-on-chip design and software stack. The goal is to create a platform for the aerospace industries implementing the open RISC-V microprocessor instruction set architecture together with specific features to address the needs of the target industries and to adopt modern commercial technology to allow leveraging technology development from other domains.

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Keywords

NOEL-V, XtratuM hypervisor, RISC-V, aerospace

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