VTT's well-proven 3 μm SOI (Silicon Over Insulator) photonic integration platform is particularly suitable for passive optical functionalities such as Multiplexers, De-Multiplexers, Power Splitters, Delay Lines, Mach-Zehnder Interferometers (MZI), also for active operations such as phase tuning through Thermo-optic Switches and optical power monitoring or high-speed detection with integrated Ge Photo-Detectors (Ge-PD) etc. In combination with integrated up-reflecting mirrors and solder coated cavities it's enabling heterogeneous integration of III-V active devices; both Wafer Level Packaging (WLP) and E/O Wafer Level Tests can be fully exploited, scaling up in volume manufacturing while dramatically reducing assembly costs. Here heterogeneous integration of 40 Vertical Cavity Surface Emitting Lasers (VCSELs) and a SOI 40:1 multiplexer Photonic Integrated Circuit (PIC) is exploited with flip-chip techniques, coupling VCSEL emitting spots on top of respective up-reflective mirrors. VCSELs can be directly modulated up to 50 Gb/s reaching a 2 T/ls full transmission capacity. Additional 40 linear VCSEL drivers are flip-chip bonded onto a suitable Land Grid Array (LGA) interposer designed to provide interconnection and thermal decoupling capabilities to the Si-PIC, realizing a very compact, thermally efficient packaging solution. The exit waveguide from the PIC is also terminated with an up-reflective mirror and furthermore coupled with a 90 deg. tilting fiber optic pigtail designed to minimize the form-factor impact, improving mechanical reliability of the overall transmitter module.

This work was partially supported by a project that has received funding from the European Union's Horizon 2020 research and innovation programme, under grant agreement PASSION No 780326.