Different approaches for copper plating have been chosen for production of heterojunction (HJT) cells following two main criteria: reliability and cost. Proven technologies from semiconductor or PCB industry based on a metal seed layer and photolithography have been successfully implemented as well as new processes with patterned seed layer or printed seed grid together with a dielectric layer as plating mask. Further cost reduction, especially for patterning, is the goal of current research activities and even direct plating of narrow lines is being developed in order to fully eliminate patterning steps. At CSEM a processing route with a sputtered seed layer and hotmelt inkjet patterning has been optimized and efficiency above 24.7% achieved on precursors from an industrial partner. Excellent module stability in extended TC and DH tests has been confirmed for interconnection with wires as well as with soldered ribbons.