Efficient execution of Artificial Intelligence (AI) workloads in edge environments with constrained energy and compute resources is crucial due to the growing adoption of edge AI across various domains. Coarse Grained Reconfigurable Arrays (CGRAs) offer a balance between hardware specialization and flexibility, enabling instruction and data parallelism by spatially distributing computation while leveraging data locality through distributed memory. CGRAs have focused on optimizing inner loops of kernels written in programming languages like C, but since AI models are expressed in different formats, new compilation techniques are necessary to fully exploit the benefits offered by CGRAs for edge AI needs. In this paper, we present our Multi Level Intermediate Representation (MLIR) based approach to extract and compile workloads from either C/C++ or Open Neural Network Exchange (ONNX) models to a RISC-V based system with a CGRA acting as an accelerator. Data Flow Graph (DFG) representations of the extracted computations are used to generate CGRA configurations through conventional mapping, and an additional MLIR-based backend enables producing binaries where the RISC-V interfaces with the CGRA through custom instructions.