Design And Analysis Of CMOS Low Noise Amplifier Circuit For 5-GHz Cascode and Folded Cascode In 180nm Technology

descriptionPublicationkeyboard_double_arrow_right Article , Other literature type 01 Nov 2018Publisher:Institute of Advanced Engineering and ScienceJournal:International Journal of Reconfigurable and Embedded Systems (IJRES), volume 7, page 149 (issn: 2089-4864, eissn: 2089-4864,

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Authors: T. Kanthi; D. Sharath; Babu Rao;

doi: 10.11591/ijres.v7.i3.pp149-156 , 10.11591/ijres.v7.i3.pp143-150

Design And Analysis Of CMOS Low Noise Amplifier Circuit For 5-GHz Cascode and Folded Cascode In 180nm Technology

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Abstract

This paper is about Low noise amplifier topologies based on 0.18µm CMOS technology. A common source stage with inductive degeneration, cascode stage and folded cascode stage is designed, simulated and the performance has been analyzed. The LNA’s are designed in 5GHz. The LNA of cascode stage of noise figure (NF) 2.044dB and power gain 4.347 is achieved. The simulations are done in cadence virtuoso spectre RF.

Keywords

Power gain, Low noise amplifiers, Noise figure

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