In this paper, we present a novel, piezoelectric actuator driver topology that combines high-voltage actuator driving in the range of −50 V-to +100 V with piezoelectric reliability. The output waveform is generated by a novel capacitor clamping circuit (patent# PCT/EP2016/066134) with programmable rise-and fall times implemented in a 0.35 um high-voltage bulk CMOS technology optimized for capacitive light-load (2 nF- to 8 nF) operation. The novel piezoelectric actuator driver consists of a negative voltage generator and a degradation regulator integrated onto a single chip. The smart driver electronics is optimized towards reliable piezoelectric operation by taking fatigue and electrical overstress into account. The novel piezoelectric actuator driver is the first step towards self-regulated electrical compensation of piezoelectric actuator degradation which promises increased actuator lifetime and reliable operation.