Reconfigurable Hardware Implementation of the Successive Overrelaxation Method
Reconfigurable Hardware Implementation of the Successive Overrelaxation Method
In this chapter, we study the feasibility of implementing SOR in reconfigurable hardware. We use Handel-C, a higher level design tool, to code our design, which is analyzed, synthesized, and placed and routed using the FPGAs proprietary software (DK Design Suite, Xilinx ISE 8.1i, and Quartus II 5.1). We target Virtex II Pro, Altera Stratix, and Spartan3L, which is embedded in the RC10 FPGA-based system from Celoxica. We report our timing results when targeting Virtex II Pro and compare them to software version results written in C++ and running on a general purpose processor (GPP).
15 pages, 5 figures, 4 tables. arXiv admin note: substantial text overlap with arXiv:1904.00629
- Lebanese German University Lebanon
- Dhofar University Oman
- Lebanese American University Lebanon
- Lebanese American University Lebanon
B.4.4, FOS: Computer and information sciences, B.5.2, D.1.3, B.6.3, B.5.1, Computer Science - Distributed, Parallel, and Cluster Computing, Hardware Architecture (cs.AR), B.4.4; B.5.1; B.5.2; B.6.3; D.1.3, Distributed, Parallel, and Cluster Computing (cs.DC), Computer Science - Hardware Architecture
B.4.4, FOS: Computer and information sciences, B.5.2, D.1.3, B.6.3, B.5.1, Computer Science - Distributed, Parallel, and Cluster Computing, Hardware Architecture (cs.AR), B.4.4; B.5.1; B.5.2; B.6.3; D.1.3, Distributed, Parallel, and Cluster Computing (cs.DC), Computer Science - Hardware Architecture
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