As two-dimensional CMOS scaling is reaching its physical limits, maintaining profitable node-to-node cost-per-transistor gains requires increasingly constraining design restrictions. To help preserve the power, performance, area, and cost (PPAC) logic roadmap several innovations are being explored, such as cell height reduction by decreasing the number of metal tracks. This allows compensating for the recent trend of a more modest pitch scaling, but it also requires fin depopulation from two fins to one fin per finFET transistor for ultra-scaled cells with reduced number of metal tracks [1,2], which impacts the device performance. As such, in order to keep the scaling gains, introduction of novel device architectures is needed, with gate-all-around (GAA) nanowire (NW) or nanosheet (NS) FETs [2-8] being regarded as the most promising finFET replacements for advanced nodes (Fig. 1). These devices provide better electrostatics allowing further gate length (Lgate) scaling, with NS offering higher current drivability (ION) per layout footprint than NW thanks to larger effective widths (Weff). Furthermore, by having the option to vary the NS Weff on the same chip/wafer, this enables additional design flexibility, typically targeting wider NS for high performance computing and narrower NS for low power applications [5,7,8]. At the same time, vertically stacking several NS enables further boosting ION at the expense of an increase in parasitic capacitance. Minimizing the latter is crucial for delivering both optimal performance and power efficiency. That can be achieved by reducing the vertical distance between the stacked lateral NS as demonstrated in Fig. 2 and via the implementation of inner spacers in-between them [2,6]. Both features introduce considerable challenges for device fabrication. However, it still shares many of the building blocks of a finFET flow thus allowing a smoother technological transition for manufacturing as compared to other device architectures. In the case of the NS vertical pitch, its shrinkage requires scaled Si/SiGe-multilayer stacks growth and thinner gate stacks that can be implemented with the guarantee of similar gate control on all NS surfaces. That has been demonstrated for a stack with an alternative, thinner (<2.5nm) n-type effective work function (EWF) metal layer yielding tight, low threshold voltage values (VT < 0.2V - NMOS), while showing improved noise and reliability behavior [9]. Another GAA device architecture, with vertical NW or NS (VNW/VNS) and vertically defined Lgate, has been shown to have the potential to enable denser and more energy efficient SRAMs and MRAMs when used as the cell transistors or selector, respectively [10-13]. In the overall scaling roadmap, the latter type of memory has been gaining increased momentum as an alternative for enabling large, ultra-high-density last-level caches for systems with reduced area and energy. Overall, GAA VNW/VNS FETs represent a more disruptive technological transition, moving from 2D to 3D layouts. Nevertheless, they can also open new scaling paths in the third dimension. In this context, the feasibility of co-integrating on the same wafer and in a cost-effective way finFETs (or GAA lateral NS FETs) for high performance logic and GAA VNS FETs as MRAM selector is evaluated by process simulations, experimentally validated for each type of devices (Fig. 3). In this scheme, cost adders were minimized by sharing the maximum number of critical process steps for both FETs. A replacement metal gate process, standardly used in finFETs and lateral NS FETs can be also advantageous for VNS FETs as it can allow shrinkage of the channel cross-section for improved electrostatics (without impacting the bottom/top S/D [14]), while also enabling new techniques for stress-induced mobility enhancement [12]. Specific for VNS FETs, a self-aligned gate electrode can be easily implemented by relying on the different oxidation kinetics of Si and SiGe and using SiGe/Si/SiGe instead of Si-only pillars. References [1] M. Garcia Bardon et al., IEDM Tech. Dig., 687 (2016). [2] H. Mertens et al., IEDM Tech. Dig., 828 (2017). [3] A. Veloso et al., VLSI Tech. Dig., 138 (2015). [4] H. Mertens et al., VLSI Tech. Dig., 158 (2016). [5] D. Jang et al., IEEE Trans. Elec. Dev., 64(6), 2707 (2017). [6] N. Loubet et al., VLSI Tech. Dig., 230 (2017). [7] S. Barraud et al., IEDM Tech. Dig., 677 (2017). [8] C. W. Yeung et al., IEDM Tech. Dig., 652 (2018). [9] A. Veloso et al., SSDM Tech. Dig., 559 (2019). [10] T. Huynh-Bao et al., SPIE Proc., 978102 (2016). [11] T. Huynh-Bao et al., DAC, 267-TY328, s13p1 (2019). [12] A. Veloso et al., IEDM 2019 (in press). [13] A. Veloso et al., SSDM Tech. Dig., 221 (2017). [14] A. Veloso et al., ECS Trans., 72(4), 31 (2016). Figure 1