This paper proposes a VLSI architecture to design a QPSK demodulator of video signals for satellite communication using baseband processing. The demodulator mainly consists of a multiplier, a root-raised cosine (RRC) filter designed using distributed arithmetic (DA) technique, and an adder to add I-channel and Q-channel signals. The main advantage of this architecture is that it does not employ any MAC unit, whose operational speed is, generally, a bottleneck for high filter throughput. Instead, it makes extensive use of LUTs and hence is ideally suited for FPGA implementation. The VHDL hardware description language is used to code the entire model. The modulator and demodulator have been coded in MATLAB in order to validate the simulation results. The simulated and MATLAB results compare favorably.