Highly reliable systems guarantee low system failure probability during its operational lifetime with the help of redundancy, which ensures system functionalities by replicating components or modules. Such modules interact with each other allowing to make decisions about the system state, and for that reason both the redundancy mechanisms and interactions between modules need to be validated to ensure correct redundancy management. The usage of a co-simulation environment that can replicate all the modules and communications between them allows to validate interactions before deployment, since it is not bound to any hardware resource. Additionally, the adoption of co-simulation allows for faster development while assisting on problem detection early on the development cycle, avoiding possible late design problems. The usage of simulation also enables early system reliability evaluations, ensuring that reliability metrics are fulfilled throughout the development cycle and preventing design reiterations later on the development cycle. Although these are great advantages, it brings a simulation challenge since most full development board simulators do not contemplate such redundancy scenarios on their tools. The aim of this dissertation is to assist reliable system development by adopting a simulation approach and extending simulator functionalities to cover the redundancy use case. Using QEMU (Quick Emulator) as the simulation tool to emulate system behaviour, three extensions were conceptualized and developed to cover features to allow for both correct redundant system validation and reliability estimations, supported by fault injection, through simulation. The resulting simulation environment assisted the development of a case study that fits under the Steer by Wire concept. The developed system resulted in a fault tolerant configuration with homogeneous redundancy characteristics. From the usage of the extensions, the resulting system software could be validated for both its algorithms and redundancy management before any hardware deployment, and it allowed for an early time to failure estimation during the design phase.