The work presented in this thesis describes the design, implementation and testing of a receiver front-end in 65nm CMOS technology for data center applications with a focus on low-power design and operation with the recently standardised four-level pulse amplitude modulation (PAM-4). The core of the receiver is based on a regulated-cascode transimpedance amplifier and Cherry Hooper post-amplifier. Series and shunt inductive peaking techniques are employed to improve the front-end's frequency response and custom designed inductors with stacked metal spirals are designed to minimize footprint. The Cherry Hooper and additional following post-amplifying stages have controllable gain to accept a wide input dynamic range. A continuous time linear equalizer can be tuned to control the receiver's frequency roll-off and limit the impact of intersymbol interference. A 50 Ohm buffer with appropriate matching termination is present to connect the front-end to external measurement equipment.\\ The receiver is heterogeneously integrated with a silicon photonic chip via flip-chip bonding and the packaged board is tested against a high-grade reference commercial receiver. The receiver board is also tested inside a full silicon photonics link with a PAM-4 capable transmitter and the performance of the full link is measured and evaluated for inter- and intra- data center scenarios. In the measurements, the challenges of accurate testing for PAM-4 operation are highlighted by comparing the measured error rates from the real instrumentation setup against those expected from an ideally simulated testbed. The fabricated receiver shows an energy efficiency of 2pJ/bit at 20 GBaud when working in PAM-4 mode and achieves a bit error rate below the required threshold of 2.2 10e-4 for forward error correction at -8dBm input average optical power.