In recent years, there has been an explosive increase in digital data generated globally, driven by various online applications such as video streaming, social media, shopping, gaming, etc. With the rise of deep learning and the Internet of Things (IoT), this trend is likely to be maintained for the foreseeable future. The major portion of the massive amount of data will be generated from endpoint devices such as PCs, phones, wearables, and connected cars. In contrast, the data will be stored in the cloud, creating capacity and energy issues in the data centers and networks. Therefore, to sustain this rapid growth of data, it is critical to develop faster and more energy-efficient communication and network system while reducing the data traffic with efficient processing. In modern communication systems, clock generation, typically done by phase-locked loops, is an important task. For the next generation high speed communication systems that are being developed these days, extremely clean clock sources with less than 100fs jitter are required. However, the generation of a clock with such low jitter involves a lot of power. Therefore, developing an energy-efficient way to generate low jitter clocks is critical. As deep learning is getting popular and the number of IoT devices is increasing, we have more data movement between edge devices and clouds. Recently, this increased data movement raised several issues, such as privacy, latency, and network bandwidth congestion. Edge computing is getting attention as a solution to these problems by moving data processing from clouds to edge devices. However, for edge computing, we need energy-efficient hardware since the battery capacity of edge IoT devices is limited. In this dissertation, energy-efficient mixed signal circuits and systems are proposed that addresses the aforementioned issues. In chapter 2, low jitter energy efficient ring-oscillator based PLL is proposed. With the proposed reference oversampling concept, the proposed PLL achieves wide bandwidth that can exceed the reference clock frequency so that phase noise from the ring oscillator is greatly suppressed. The proposed PLL achieves a 500fs rms jitter with 3.6 mW power consumption, which translates to 240dB FOM. The PLL also achieved a -80 dBc reference spur thanks to the reference oversampling. Chapter 3 proposes a 67fs rms ultra-low jitter LC-oscillator based PLL using the reference oversampling techniques. The reference oversampling technique simultaneously achieves low in-band noise and wide bandwidth at the same time, achieving sub-100fs low jitter with excellent power consumption. LC-DCO structure for the reference oversampling and optimal DCO tuning word control scheme is also proposed. This work achieved 67fs rms ultralow jitter with 5.2 mW power consumption, -256 dB FoM power efficiency. Finally, in chapter 4, a low power keyword spotting system with a dynamic neural network is proposed. The proposed work adopts the skip RNN algorithm to adaptively power gates the entire system, including the analog front (AFE) end and the digital back end. The proposed AFE structure with a dc coupled first stage LNA and switched capacitive feedback resistors achieves less than 1ms settling time, enabling fast on/off. The proposed work demonstrates 1.5 uW power consumption.