This talk describes research underway in the ECE Department to develop reconfigurable computing technology for spacecraft. Today’s spacecraft, whether Earth orbiters or planetary probes, serve primarily as sensing and communicating nodes. As sensors grow more complex and the quantity of data mushrooms, computational and communication requirements to support space missions keep growing. More ambitious deep-space missions, including planetary rovers, require greater autonomy, with greater sensing, decision-making, and control capability. But the demands of the space environment preclude throwing more conventional processing power at the problems. The Embedded Micro-Nano Systems group at the University of Idaho is developing as suite of technologies to enable high throughput with minimal power consumption in a technology that is resistant to the destructive effects of radiation. This talk will present a systems-level view of this work, embodied in the Reconfigurable Computational Platform. Conventional von Neumann computers, such as desktop microprocessors and digital signal processors (DSPs), execute instructions sequentially on fixed hardware. The designer achieves computational flexibility by organizing the instructions into a program; the order of the instructions determines the behavior. The throughput is limited by the speed with which this computer can execute one instruction. In contrast, reconfigurable computing provides many computational nodes, or processing elements, enabling many different computational tasks to be carried out simultaneously. Computational flexibility comes from reconfiguring the hardware to perform different parts of a computation. Our approach implements a synchronous dataflow model. Processing elements can be reconfigured to perform different tasks, and a reconfigurable interconnect establishes a different dataflow topology, depending on the computational problem. Advantages to this approach include: 1. Maximizing throughput through scaling, with tens of hundreds of processors working in assembly line fashion 2. More efficient use of power by move computational resources from control and memory to data path 3. Reduced clock speed, which reduces power consumption and greatly reduces signal integrity problems 4. Thanks to reduced clock speeds, reconfigurable candidates can be implemented in radiation-hard by design (RHBD) technologies Major challenges include 1. Develop efficient reconfigurable processing nodes 2. Develop efficient reconfigurable interconnect 3. Develop suitable software to map computational problems onto the synchronous dataflow model 4. Implement the hardware in a Radiation Hard By Design technology This talk will describe the Reconfigurable Data Processing Platform project, and discuss our approach to these challenges. Thursday, January 19, 2006 Engineering-Physics 122 3:30 PM ________________________________