This thesis outlines the design, layout and characterization of an application specific integrated circuit (ASIC) and a printed circuit board (PCB) designed to discretize an input signal and read out the data at a user desired interval to replicate the input signal at a lower frequency or pulse rate with no quantization error. The ASIC for this task utilizes 128 individual capacitive storage cells to capture data at approximately 200 ps intervals, thus the chip can capture approximately 25 ns of an input signal. The read out rate can be adjusted to the desired rate by the user by changing the rate of the input clock signal to the PCB. The circuit dissipates no appreciable DC power and uses a 5 V power supply. Each of the capacitive cells on the chip is driven by a transistor receiving a buffered (delayed) trigger signal, the trigger signal controls the data capture process. On the falling edge of the trigger the transistor shuts off and the charge from the input signal is captured on the capacitor. The clock signal is propagated to the next cell through another buffer which provides the necessary delay. The output stage is controlled by a PMOS transistor that is driven by the capacitor; this transistor is fabricated in a separate n-well to eliminate the body effect. The PMOS transistor is connected to the output through an NMOS switch that is connected to a pullup resistor, the switch is controlled with a select signal that allows the data to be read out. During the read out process the select signal is driven high for each stage sequentially, when the switch is activated the charge stored on the capacitor drives the PMOS transistor and sets the output current creating a current controlled voltage drop across the pullup resistor that replicates the input signal.