In this paper, a monopole patch antenna is designed, and the structure of the antenna is analyzed. The manufacturing process adopts TSMC 0.18 μm CMOS process technology. An artificial magnetic conductor (AMC) on the M1 layer is proposed in this paper to increase the radiation gain and reduce the reflection coefficient (S11) magnitude for impedance matching and antenna performance. This method can make up for the radiation efficiency and benefits of the antenna-on-chip that are affected by the high dielectric constant and low resistivity of the silicon substrate of the CMOS process. The antenna designed in this paper obtains a simulated bandwidth of 37.5 GHz to 69.5 GHz using the Electromagnetic Simulation Software, and the fractional bandwidth of the design is 60%. Among them, 62 GHz shows a maximum gain value of −2.64 dBi. Actual measurements have confirmed that the reflection coefficient of the antenna on the chip proposed in this paper is the same as the simulation trend, and a wider bandwidth is obtained from 20.9 GHz to 67 GHz, with a fractional bandwidth of 104.89%. This bandwidth covers millimeter wave 28 GHz, 38 GHz, and 60 GHz application frequencies.