A novel frequency-to-voltage converter (FVC) based phase-locked loop (PLL) is proposed to overcome the inability of an FVC-based frequency-locked loop (FLL) to lock phase. The proposed dual-loop PLL adds variable phase-locking capability, such that the phase locking angle can vary from 0o – 360o. The additional variable phase-locking can be applied in data communication in the form of phase modulation. The design is targeted for a 0.5-µm CMOS process. The proposed design generates a 480MHz clock from a reference clock of 15MHz. In simulation, the proposed PLL locks within 3.56 µs while consuming 1.61 mW of power.