Abstract : This report describes the results of a study on the chip design of a low-power filter, using state-of-the-art CMOS technology. The filter is for speech applications and is specified to have 1024 type with programmable weights and linear phase. The chip implementation is to have a word length of 8 to 12 bits and consume a maximum of 2.0 mA at 3.6V. Included are current capabilities of CMOS/SOS/bulk, technology, and in particular, the Hughes VHSIC CMOS process. The architecture of the filter is discussed and estimates are made for the power consumption, speed, device count, and projected chip size of the filter implementation. A comparison of a multiple tape and a single tape implementation of the filter is also presented in terms of power consumption and operational speed.