The demand for telecommunication bandwidth continues to grow rapidly, fuelled by increasing numbers of users, increasing time per user, and increasing connection speeds. Optical fibres can cope with this bandwidth explosion. With ultra-long-haul optics driving photons across the continent Without regeneration, lighting petabits per bundle will soon be practical. But while the optics can handle petabits of traffic, today's, routers still require converting the traffic to electrons to re-route the traffic at each hop, an average of ten times across the network core. If a router could scale to match the optics, packets could be routed only once onto a wavelength that would be optically transported to its destination, city with no need for intermediate electronics. Hyperchip has developed such a router based on a system architecture that scales to support up to petabits of aggregate bandwidth. A router consists of complex software for maintaining routing and forwarding tables, dedicated hardware to parse packets and forward them according to those tables, a switch fabric to transfer packets from interface card to interface card, and traffic managers to optimise traffic flow, through the switch fabric. While some hardware is implemented in reprogrammable logic, the switch fabric hardware must be in leading edge ASICs for performance, density and minimal power consumption. The paper covers the techniques used and the lessons learned in bringing such a large ASIC and complex FPGAs to fruition on such a short timetable, and how synthesis and simulation were aggressively employed to ensure first-pass silicon and system success.