Dynamically reconfigurable architectures allow sharing of hardware resources, which is particularly beneficial for small low-end FPGAs. Based on the online modification of parts of the circuit, these architectures require partial reconfiguration of the chip. Reducing resource availability or usage comes at the cost of a performance penalty affecting execution time. The challenge lies in bitstream management, especially for complex applications that often exceed the internal memory capacity of the FPGA (BRAM). Consequently, the time penalty arises from the need to retrieve partial bitstreams from external memory (e.g., often a DDR) each time it is necessary. Current state-of-the-art reconfiguration controllers are limited to a throughput of 400 MB/s, significantly penalizing reconfiguration times and making dynamic reconfiguration unattractive for real-life applications (e.g., video processing, machine learning applications, and continual and federated learning for embedded systems). This article introduces a novel partial reconfiguration controller architecture that achieves a throughput of up to 1.396 GB/s, a 3.49× acceleration over existing controllers. The reduced reconfiguration time allows the practical use of dynamic reconfiguration with fewer performance penalties. Additionally, the article compares various reconfiguration controllers in terms of time penalties and offers a tradeoff between algorithm complexity, FPGA resources, and performance.