Optical Character Recognition (OCR) techniques are widely used in data/text entry, process automation. Decades of research efforts have made the accurate recognition of typewritten text largely accepted as a solved problem. Driven by practical usage demands, the low complexity and high performance implementation techniques of OCR systems are studied. Recent research shows that it may not be possible even for a simple OCR to run on a portable device without a specialized digital signal processor. In this paper, we present a highly data-parallelized implementation of OCR for typewritten text onto the linear processor array of the Xetal chip. Besides the preprocessing stage, the most computation intensive part of OCR recognizing individual characters is highly parallelized onto the Single Instruction Multiple Data (SIMD) engine of the Xetal chip, which can process a VGA-resolution text frame within one tenth of a second. In addition, different parallelization schemes are explored to make trade-off between the degree of parallelism and the costs of preprocessing to reorganize data to feed the SIMD engine and post-processing to assemble and collect results. The exploration of parallelized OCR application brings additional performance gain when mapped onto the linear processor array of the Xetal chip.