This paper presents a power efficient design of All Digital Phase Locked Loop (ADPLL). The proposed ADPLL uses power optimized digital loop filter instead of the conventional one. The power optimization of digital loop filter is carried out with the aid of clock gating technique without degrading the performance of the overall system. The proposed architecture is implemented using Verilog HDL and is synthesized using Cadence RTL compiler using gpdk 45 nm technology. To validate its functionality, verification and simulation is done by using the Cadence IES (Incisive Enterprise Simulator) tool. The power consumption of this ADPLL is 0.704 µW at a center frequency of 625 KHz. The total chip area is 207 µm2.