In this paper, we proposed a fractional frequency synthesizer based on all digital phase-locked loop (ADPLL). A new phase frequency acquisition mode is involved with an initial half-step size to speed up the convergence in phase and frequency comparisons. The dual modulus frequency divider by four or five is applied to perform the various fractions. The frequency synthesizer is implemented with TSMC 0.35 /spl mu/m 1p4m CMOS technology. Experimental simulations show the more encourage results. The chip area is lower to 1.3 /spl times/ 1.3 mm/sup 2/, locked time is less than 20 reference cycles, power consumption is only 15 mW, and the jitter is 90ps at 300 MHz.