Growing test data volume and excessive test power consumption in scan testing are both serious concerns for the semiconductor industry. This paper presents a method to simultaneously reduce test data volume and test power utilizing clock gating. This is achieved through not clocking a high proportion of scan chains during both scan shift and test response capture. Reducing the number of scan chains shifted during scan load can be expected to permit higher scan shift frequency thus reducing the test time. Reduced test data volume can be expected to permit fewer tester channels for testing which can increase the number of chips tested in parallel. Experimental results presented for industrial circuits demonstrate that on average a factor of 1.98 and 4 reductions in test data volume and test power, respectively is achievable using the proposed method.