Dynamic I/sub dd/ test techniques are obtaining more attention from both academia and industry, because of their ability to further improve product quality beyond tests based primarily on I/sub ddq/ test and other traditional test techniques. Normal process variations in wafer fabrication decrease the defect coverage and affect the application of dynamic I/sub dd/ test techniques. Energy Consumption Ratio (ECR) test, a recent test metric based on dynamic currents, shows its tolerance to process variations, over other dynamic test techniques. We investigate this technique as a method of providing additional test coverage to production wafers that were fabricated using two different planarization technologies. One set was fabricated with a Spin-on-Glass (SOG) planarization technology, and the other set with Chemical Mechanical Polishing (CMP). The SOG wafers used in our experiments contain defects known as "poisoned vias." We show that the ECR is effective in detecting defects of this type where other traditional test methods are not.