Results from a novel quasi-SOI CMOS architecture fabricated on bulk SI are reported for the first time, demonstrating its viability as an alternative device for the nanometer regime. All of the processing is basically compatible with the conventional CMOS technology. The short-channel effects and the drain-induced barrier-lowering effects can be effectively suppressed by the "L-type" insulator surrounding the source/drain regions. In addition, quasi-SOI MOSFETs can be more tolerant of process- induced variation for the deep nanometer regime. The quasi-SOI MOSFET can be considered as one of the promising candidates for highly scaled devices.