New results are given on the phenomenon of false lock in second-order, Type I PLLs (phase-locked loops) with a constant frequency reference of /spl omega//sub i/ and a VCO (voltage-controlled oscillator) quiescent frequency of /spl omega//sub o/. Of interest here is the stable false lock state whose frequency error approaches /spl omega//sub i/-/spl omega//sub o/ as loop gain /spl delta/ approaches zero. Once the loop is in this stable false lock state, its closed-loop frequency error decreases with increasing /spl delta/ until a point /spl delta//sub 1/ is reached where the false lock state can be continued no further. Saddle-node bifurcation is shown to occur at /spl delta//sub 1/. The stable false-lock state is a stable hyperbolic limit cycle which bifurcates from /spl delta//sub 1/, and it can be continued on 0 /spl les//spl delta//spl les//spl delta//sub 1/. A second limit cycle bifurcates from /spl delta//sub 1/; it is unstable; and it can be continued on an interval /spl delta//sub 2/ 0. Both cycles become semi-stable at /spl delta//sub 1/, and neither can be continued for /spl delta/ > /spl delta//sub 1/. Two numerical algorithms are discussed which are useful for analyzing the false locked PLL under consideration. >