Full duplex wireless has drawn significant interest in the recent past due to the potential for doubling network capacity in the physical layer and offering numerous other benefits at higher layers. However, the implementation of integrated full duplex radios is fraught with several fundamental challenges. Achieving the levels of self-interference cancellation required over the wide bandwidths mandated by emerging wireless standards is challenging in an integrated circuit implementation. The dynamic range limitations of integrated electronics restrict the transmitter power levels and receiver noise floor levels that can be supported in integrated full duplex radios. Advances in compact antenna interfaces for full duplex are also required. Finally, networks employing full duplex nodes will require a complete rethinking of the medium access control layer as well as cross-layer interaction and co-design. This article describes recent research results that address these challenges. Several generations of full duplex transceiver ICs are described that feature novel RF self-interference cancellation circuits, antenna cancellation techniques, and a non-magnetic CMOS circulator. Resource allocation algorithms and rate gain/improvement characterizations are also discussed for full duplex configurations involving IC-based nodes.