Challenges in analog-to-digital (A/D) conversion for future scaled complementary metal-oxide-semiconductor (CMOS) technologies are investigated. The analysis of a figure of merit (FOM) that accounts for energy per conversion step indicates that op-amps are one of the most significant performance bottlenecks. New mixed-signal circuit architectures, which are more suitable for A/D conversion in scaled CMOS technologies and are more energy efficient than traditional architectures, are described. These circuits sense the crossing of virtual ground with comparators or zero-crossing detectors instead of forcing the virtual ground with op-amps. The FOM derivations for the comparator and zero-crossing based circuits indicate potentially a large improvement over traditional op-amp based circuits. The designs and experimental results of analog-to-digital converters based on a prototype comparator and zero-crossing are discussed in detail.