Although Moore's law has been the most pursued principle since ever; it has become troublesome to apply that on the traditional MOS structures in today's scenario. Striking increment in the subthreshold leakage current, and various other disadvantages like gate-dielectric leakage gate-induced drain leakage (GIDL) are the major factors which limit the scaling of the MOS devices. And so, researchers are in need of novel ideas and mechanizations. Of so many of the lately surfacing devices, Carbon Nanotube Field Effect Transistor (CNFET) is becoming the hopeful alternative of MOSFETs, owing to its enviable properties of electrical, physical and mechanical factors. In this paper, a circuit based technique to lessen the unfavorable effects on the design metrics such as margin for write and read operation of MTJ memory cell is proposed. The effects of process, voltage and temperature (PVT) variations are investigated. The study is based on Monte Carlo simulations in a HSPICE environment, using a Stanford CNFET model. In this work, 2-CNFETs, 1-MTJ based STT-MRAM bit cell based on power gating technique is suggested to improve its performance metrics.