A new electronic design for a TCN (train communication network) bus is presented in this paper. Based on top-down philosophy and focused on system on a chip strategies, various of its modules are expected to be reused in some other designs for complex communication circuits. In order to verify the Class 1 device proposed for MVB (multifunction vehicle bus), its final description has been synthesized. The advantages and problems encountered are described. The process proposed to refine system description is based on these three models: an algorithmic model using a high level language, a functional model in VHDL and the final model for synthesis, also in VHDL. The simulation and verification process has been accounted from the initial algorithmic model, so much time has been saved. Translation between algorithmic and functional models is straightforward because both descriptions have been intentionally made similar, but much care must be taken to take advantage of concurrency in HDL. The last model for synthesis conversion is based on structural division, by making smaller blocks from the functional description. Exhaustive simulation using specific testbenches has validated each model. Although design flow is generic enough to be used in other cases, such a device is a good test for this methodology. Bottom-up design methodology and a multichip approach were used during an initial experience in MVB device synthesis.