An improved voltage tripler with a symmetrical stacking charge pump has been proposed. A pre-charge of parasitic capacitances has been added in this improved structure. Consequently the output voltage loss is reduced by a factor of 2. An optimised design of the improved voltage tripler for applications with a resistive load has been thus developed in terms of the circuit die area. The analysis shows that only with the optimised design the improved voltage tripler can offer the maximum output voltage of the theoretical limit, 3Vdd. A design example has been given.