In this contribution, the development of the dynamic threshold voltage (DT) MOSFET is reviewed. The forward-biasing of the source-substrate junction was proposed for the first time in 1984 as part of an early strategy to improve the MOSFET performance when scaled. This led to the design of a quarter-micron technology, operating at 77 K, using a 0.6 V voltage supply and with the substrate connected to a fixed forward biasing potential. Ten years later, the operation of the gate controlled lateral bipolar transistor (GC-LPNP) and the SOI MOSFET with the substrate tied to the gate terminal both operating as dynamic threshold devices, were demonstrated. The SOI DTMOS was the best alternative for ultra low power CMOS applications and the GC-LPNP was used for some compact low power analog circuits. Aggressive technological improvements led to successful fabrication of bulk DTMOS, whose current representatives show impressive figures of merit regarding gate delay-power consumption products, well above those of conventional CMOS.