Low power signal processing functionality is required for wireless sensor network nodes due to their limited battery life. Previously, we have proposed a reconfigurable array of DSP acceleration functional units for such a sensor node. The array maximizes operating life by matching system power consumption to available energy through power scalable approximate signal processing. This paper presents the detailed architecture and implementation of the functional unit in the array. The use of low power building blocks and bit serial processing enables energy scalable implementation of several DSP functions. Post-layout simulation of a semicustom implementation in 0.25 mum CMOS technology demonstrates a factor of three power scalability with input bitwidth for an FIR matched filter.