This paper describes a digital-to-time converter (DTC) architecture that can be used as interpolator in a time-to-digital converter (TDC). The new architecture of the DTC achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range. The propagation delay adjustment is implemented by digitally controlling both the unit load capacitors and the discharge current of the load capacitance using current DAC and differential current switch. The proposed DTC achieves 610 fs resolution and ∼2.5 ns dynamic range. The total simulated power consumption is 25.53 mW with 8 MHz conversion rate with 3 V supply. The design was simulated using a 0.35 µm CMOS process.