Wireless communication systems targeting miniaturized sensor microsystem networks are characterized by their restricted power and area constraints. DS-SS systems are well suited for such applications. When considering the design of a communication system for such a network, the receiver is the key critical block. This paper discusses the impact of input data characteristics and resolution together with internal data path complexity on area and power performance of the receiver. A number of transmitter/receiver architectures have been constructed and their power/area have been analyzed. Up to 59% and 11% savings in area and power respectively could be achieved by optimizing input data size and internal register width for a particular application while maintaining signal quality.