A 25Gb/s low noise 65nm CMOS receiver tailored to 100GBASE-LR4

descriptionPublicationkeyboard_double_arrow_right Article , Conference object 01 Sep 2012Publisher:IEEEJournal:2012 Proceedings of the ESSCIRC (ESSCIRC)

Authors: Dan Li; Gabriele Minoia; Matteo Repossi; Daniele Baldi; Enrico Temporiti; Andrea Mazzanti; Francesco Svelto;

doi: 10.1109/esscirc.2012.6341298

A 25Gb/s low noise 65nm CMOS receiver tailored to 100GBASE-LR4

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Abstract

Shunt-feedback TIAs suffer from a trade-off between noise and bandwidth. In this work we propose a two stage 25Gb/s front-end, made of a low noise narrow-band TIA followed by an equalizer aimed at restoring the required bandwidth, providing a 4x noise power reduction compared to a traditional design approach. A 65nm receiver cascading the proposed front-end, the limiting amplifier and a buffer, tailored to 100GBASE-LR4, demonstrates a gain of 83dBΩ, an input referred equivalent rms noise current of 2.44μA and an electrical analog bandwidth tunable between 10.6GHz and 18.2GHz. The power consumption is 93mW with a FOM of 2066GHz·Ω/mW.

Related Organizations

University of Pavia
Italy
STMicroelectronics (Switzerland)
Switzerland

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