Through-Silicon Via (TSV) plays an important role as the interconnects in accomplishing three-dimensional miniaturization of electronic device. Due to large mismatch in Coefficients of Thermal Expansion (CTE) between metal via (usually copper) and silicon substrate of TSV, induced thermal stress would lead to electrical performance and various reliability issues, such as device characteristics deviation. In this paper, FEM simulation was carried out for thermal stress analysis of TSVs. TSV cross-section stress measurement by polarized Raman spectroscopy were performed under three temperatures. With offsetting the measured residual stress at room temperature, we report that both radial and axial thermal stresses in simulation agree well with measurement data, which validated the simulation methodology. With this validated simulation, we revealed that the methods as parylene substitute of SiO 2 as dielectric layer and annular structure lose the efficacy for thermal stress reduction with TSV scaling down. A novel Annular-Trench-Isolated TSV is proposed to solve the thermal issues in 3D IC integration from a brand new point view of stress distribution optimization. Annular-Trench-Isolated TSV, as copper core, silicon ring layer, SiO 2 layer, reduces thermal stress in silicon substrate by concentrating the stress to copper/silicon interface inside TSV, which is suitable for stress sensitive device. Furthermore, the advantage of stress reduction in silicon substrate by silicon ring layer enhances with TSV scaling down.