Abundant three-dimensional packaging technologies were developed for chip-to-wafer or wafer-to-wafer bonding, which employed through silicon interconnect to achieve the shortest circuit design of inter-chip or inter-wafer. In this paper, we focused on the wafer stacking technology by introducing silicon-through three-dimensional interconnect. The innovative structure as shown here is a new concept of three-dimensional integration of via-preformed silicon through wafers. Compared to the recently research of 3D chip-to-wafer or wafer-to-wafer stacking, it demonstrated of wafer stacking using this reliable design. The wafer/chip thickness used here was 150 /spl mu/m and down to 50 /spl mu/m. The result shows the benefits of this structure can provide more reliable wafer stacking without any voids. Not only the assembly accuracy of the joint between two chips/wafers can be reduced, but we can get improvement of the yield of the whole wafer during the wafer bonding process, even the thickness uniformity of the wafer is higher than 10%. The experiment confirmed that this newly low-cost interconnect technology could be a good candidate for both wafer stacking application and 3D SiP module.