Keccak hash function has been submitted to SHA-3 competition and it belongs to the final five candidate functions. In this paper FPGA implementations of Keccak function are presented. The designs were coded using HDL language and for the hardware implementation, a XILINX Virtex-5 FPGA was used. Some of the proposed implementations use DSP48E blocks in order to accelerate the designs execution. So, comparisons between the proposed designs in terms of time performance and FPGA resources are given in order to examine the efficiency of the using DSP48E blocks. Also, comparisons with previous published works are provided.