Nanoscale systems are characterized by increasing parameter variations as well as an increasing susceptibility to soft errors. Transient errors during system operation are no longer restricted to memories but also affect random logic, and robust circuit design has thus become a major concern for system developers. Self-checking circuits rely on redundancy to detect and compensate errors on-line. They are usually designed to reach the totally self-checking goal (TSC), i.e. an error is detected as soon as it corrupts the system data for the first time. However, during synthesis and optimization self-checking properties can be destroyed. This presentation shows how automatic test pattern generation (ATPG) can be used to analyze self-checking properties. While fault-secureness and self-testability can be verified by using standard ATPG tools for appropriate test benches, the analysis of strongly fault-secure circuits is more challenging. Here it must be proven that the circuits have a secure behavior even in the presence of fault accumulation, which requires the analysis of all possible fault sequences. To speed up the complex analysis of multiple faults we develop rules to derive detectability or redundancy information for multiple faults from the respective information for single faults. If a circuit cannot be proven to be fault-secure, the proposed method allows grading the “extent” of strong fault-secureness given by the implementation.