A description is given of the scalar supercomputer and of a particular implementation, the Prisma machine. The performance goal is a sustained rate of 150 million instructions per second, with matched memory size and I/O capabilities. The machine will be binary-compatible with other computers implementing the SPARC architecture. To obtain this level of performance, designers are implementing the computer with gallium arsenide integrated circuits. The circuit have a typical delay of about 150 ps, allowing the use of a system clock of around 4 ns. Using a proprietary packaging technology, the entire CPU may be packaged in a few cubic feet, minimizing interconnection delay. The machine will also support IEEE floating-point arithmetic, providing a more secure numerical foundation for complex computations than machines which are unable to support the standard. >